The fabrication of semiconductor devices includes a complex array of fabrication processes. By example, in known fabrication process of CMOS devices, several lithographic steps are required to build the gate stacks for the nFET and the pFET. These lithographic steps add additional fabrication costs to the building of the device, in addition to leading to alignment errors.
More specifically, lithographic steps to form the gate structures present alignment errors typically leading to stringers formed in the shallow trench isolation structure (STI) between the nFET and pFET regions of the device. These stringers, in turn, lead to performance issues related to the device. As should be understood, stringers are formed by damage which occurs to the surface of the STI during etching, stripping and subsequent deposition processes of the gate structures.
More specifically, in forming a CMOS device, an STI is formed in the substrate. After several layers building up the structure, e.g., sacrificial oxide layers, a poly layer, etc., a photoresist litho layer (mask) is formed over the pFET region of the structure, which is used to protect the pFET region during a subsequent poly removal process. After etching and stripping processes, a thin oxide layer is grown over the nFET region and a dielectric layer and metal layer are formed over the oxide layer.
A mask is then formed on the metal layer over the nFET region. As it is not possible to precisely align the mask over the nFET region, the device is designed with a margin of error. Due to this margin of error, the mask can either overlay onto a pFET side of the STI or, alternatively, extend only partially over the STI on the nFET side. In the latter situation, a gap is formed in the structure exposing the underlying metal layer on the STI. During the etching process, the exposed metal layer and dielectric layer in this gap are etched away, leaving behind a separation space, i.e., an exposed portion of the STI. During the resist strip (or even the etching), the exposed portion of the STI region becomes damaged. This damaged portion becomes filled during the poly deposition process to form the gate stacks of the nFET and pFET. This filled portion is known as a stringer which negatively affects the device performance.
Basically, as should be understood, the stringer is formed due misalignment of the block mask over the nFET region. This block mask not only results in the misalignment and hence the subsequent formation of the stringer, it also adds additional processing steps and costs to the manufacturing process of the device. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.